Review of FPGA based Design of Low-Power Router

Authors- Putrevu Voshanavi, Yenni Ajay, Ponnana Triveni, Padala Sri Sai Nandu, Sanapathi V V S S Siddartha, Mohd Rizwan Uddin Shaikh

Abstract-The paper discusses an FPGA-based approach to designing routers for efficient data packet forwarding across networks. It introduces the router’s architecture, which uses Verilog HDL and Universal Verification Methodology (UVM) for design verification. The proposed design focuses on reducing power consumption while maintaining high performance through the use of synchronous FIFO buffers, Finite State Machines (FSM), and a register-based approach for packet handling. The router operates at the network layer, ensuring data integrity through error checking mechanisms such as parity verification. The survey also outlines a verification strategy involving UVM-based test benches and RTL linting to identify functional bugs early, ensuring a robust, low-power router design suitable for Network-on-Chip (NoC) platforms.

DOI: /10.61463/ijset.vol.12.issue5.304