International Journal of Science, Engineering and TechnologyAuthors: Assistant Professor Atul S. Chaudhari, Aayush Mahesh Kotwal
Abstract: The continuous downscaling of semiconductor tech- nology has increased the need for reliable timing estimation and optimization in modern VLSI design. Conventional timing analysis methods depend heavily on post-routing data, which provides accurate results but demands substantial computation and slows down the overall design cycle. To overcome these limitations, recent work has moved toward incorporating deep learning models into earlier stages of the flow particularly during placement to enable faster and more predictive timing assessment. Prior studies have contributed in areas such as statistical timing analysis under process variability [1] and CNN- based frameworks for routability and power prediction, including RouteNet [4], PowerNet [2], and PROS [3]. However, these approaches operate mainly after placement or during routing, which restricts their usefulness for identifying timing issues at an early stage. The DTOC-P framework [5] marks an important shift by combining deep learning–based pre-route timing prediction with optimization capabilities of commercial EDA tools. It estimates arc delays and slew values during placement, pinpoints potential critical paths, and applies targeted refinement through iterative feedback using techniques such as buffer insertion and gate sizing. Additional features like continual learning and anomaly detection further improve its adaptability and reliability. This review paper provides an in-depth discussion of deep learning approaches applied to timing prediction and optimiza- tion, examining their methodologies, benefits, and challenges in comparison with DTOC-P. The analysis underscores how early-stage prediction and intelligent automation can shorten the timing-closure process, enhance accuracy, and reduce computa- tional effort in advanced technology nodes.
