International Journal of Science, Engineering and TechnologyAuthors: Utkarsh Das, Vinod Solanki
Abstract: In the modern design of System on Chip (SoC), various functional units are integrated onto a single chip, requiring a high-performance bus to enable smooth communication between various units of the SoC design. The AMBA AHB protocol is widely used in the VLSI industry due to the high-speed communication, pipelined architecture, and efficient implementation of read/write operations. However, the traditional approach of design verification using Verilog/SystemVerilog is often time-consuming, less efficient, and may not provide comprehensive functional coverage of the design under test. Therefore, this work focuses on the implementation of the AHB protocol using a single master and single slave configuration and the Universal Verification Methodology (UVM) to achieve the efficient verification of the protocol. The proposed methodology utilizes the key components of the UVM library such as the sequencer, driver, monitor, scoreboard, and agent components with the support of the Transaction Level Modeling (TLM) concept to achieve the desired level of reusability of the test cases. Constrained Random Stimulus and Functional Coverage are also employed to assess the performance of the proposed verification methodology. The QuestaSim tool was used for verification tasks in the design, simulation, monitoring, and coverage analysis. The results show correct operation of read and write transactions, correct signal interactions, and correct validation of protocol operation through waveform analysis. Coverage results show that all functional scenarios are adequately tested, and verification is complete. This approach demonstrates a scalable, reusable, and efficient verification methodology, reducing verification time and improving reliability before hardware implementation.
