International Journal of Science, Engineering and TechnologyAuthors: Assistant Professor Deepak Sharma, Ms. Narayani Shanbhag, Ms. Rashmi Kalkapur, Ms. Sanjana Mahantesh. Koladur, Ms. Varshini Fakkirgouda. Patil
Abstract: In modern digital systems, priority encoders play a vital role in resolving multiple simultaneous requests by assigning a priority to each input. This work focuses on the design and implementation of a 4:2 Priority Encoder using 45nm CMOS technology, targeting low-power and high-performance applications. The encoder accepts four input lines and provides a 2-bit binary code corresponding to the highest-priority active input, along with a valid output signal to indicate the presence of any high inputs. The design process was carried out using the Cadence design suite, leveraging Virtuoso for schematic capture, and Spectre for circuit simulation. Transistor-level design methodologies were applied to optimize power, delay. The design achieved minimal propagation delay and power consumption, making it suitable for integration in processors, interrupt controllers, and other digital subsystems where fast and efficient signal prioritization is required. Furthermore, the physical design was verified through. The successful implementation of the 4:2 Priority Encoder using 45nm technology showcases the viability of compact digital logic design in advanced nodes and provides a reference for future low-power VLSI designs.
