DESIGN AND VERIFICATION OF LOW DROPOUT REGULATOR USING 45nm IN CADENCE

Authors: Assistant Professor Mr. Deepak Sharma, Shreedevi Sidnal, Sandhya Naik, Bhoomika Hiremath, Asfiya Sheikh

Abstract: This project involves the design and verification of a Low Dropout (LDO) Regulator using 45nm CMOS technology within the Cadence design environment. The main goal is to develop a power-efficient and high-performance voltage regulator suitable for modern low-power integrated circuits. The design focuses on achieving low quiescent current, high power supply rejection, and stability across different operating conditions. Key performance parameters such as line regulation, load regulation, and transient response were analyzed in detail through simulations. The LDO was tested under various input voltages and load currents to evaluate its performance and robustness. Compensation techniques were applied to ensure stability over process, voltage, and temperature variations. Simulation results show that the LDO performs reliably, with fast response and minimal voltage deviations. Overall, the design is well-suited for applications in nanoscale, low-power electronic systems like mobile devices.

DOI: http://doi.org/