Design of Area Efficient, Low Power, High Speed 8-Bit Array Multipliers by Using Transmission Gate Logic

Design of Area Efficient, Low Power, High Speed 8-Bit Array Multipliers by Using Transmission Gate Logic

Authors- P.G Scholor Seera Reshma, Assistant Professor Velaga Suryakala/span>

Abstract-The multiplier is the most basic unit of an arithmetic circuit which is predominantly used in digital processing units and several integrated circuits. The efficiency of a processing unit is measured by its speed and power consumption. The multiplier circuit involves an extensive use of adders that generally add to its hardware complexity and thus is a major bottleneck to fast processing and also consumes high power. Thus it becomes critical to improve speed and reduce power consumption in the multiplier module. The conventional multipliers implemented using the CMOS and Transmission Gate (TG) technologies and their combination versions, albeit showing improved speed and low power consumption, still suffer from high hardware complexity. This project proposes the design of an 8-bit Array multiplier. The key idea here is to use the power efficient TG technology based 1-bit hybrid full adder within the popularly used array and Wallace tree multipliers to obtain a new multiplier design with fewer transistors and full output voltage swing. The proposed designs are implemented using Tanner EDA with 90nm technology and simulation results show substantial improvement when compared with the state of the art.

DOI: /10.61463/ijset.vol.12.issue5.280