DESIGN OF 8-BIT SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER USING CADENCE TOOL

Authors: Assistant Professor Deepak Sharma, SRISTHI S SUGATE, POOJITHA J N, SUSHMEETA M BADLI, VARSHA U HEGADI

Abstract: This project proposes a 1V 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology. The asynchronous SAR ADC system consists of an internal-clock generator, a bootstrapped sample-and-hold switch, a capacitive digital-to-analog converter (DAC), a dynamic comparator, and a SAR logic. Taking a 64-point FFT on the output of the SAR ADC and with an input signal of 1.2V differentially, the maximum ENOB achieved at 20 MHz. This SAR ADC system can be used in systems that mainly require low power with medium resolution and medium speed like in computing-in-memory cores for AI applications and in sensors for biomedical applications.