International Journal of Science, Engineering and TechnologyMicro-Architect on RISC-VISA
Authors- Dhanush S, Deepan R, Chandru M, Geethalakshmi M
Abstract-The major problem with the ISA architecture is its power consumption ratio for the ALU operation .It has a MUX Combinational circuit for their memory access purpose . Comparing with other logic gates mux have additional logic gates which is needed for the purpose of path selection leading to consume more power . As an alternative we use more multipliers but the X factor want to consider was the execution time must be very quick and efficient to my signed numbers . Our approach uses Baugh – Wooley algorithm which over comes all the drawbacks of other multiplier and has nearly of 24.32% power reduction .This can be measured in two ways as the time consumption can also be calculated by the RTL design and the power efficiency can be calculated by the synthesis method where can generate power reports.
DOI: /10.61463/ijset.vol.13.issue2.201
