AI-Based Hardware Encryption And Threat Detection Using Zynq PS-PL Architecture

Authors: Gokularangan V, Narsingam K, Dr. V. Ramesh Kumar

Abstract: This paper presents a comprehensive technical account of an AI-based hardware encryption and threat detection system implemented on the Xilinx Zynq-7000 SoC using the ZedBoard development platform. The design exploits the tightly-coupled Processing System (PS) and Programmable Logic (PL) of the Zynq architecture to deliver real-time security capabilities operating at hardware speed. The core innovation is the fusion of a lightweight AI decision model (threshold-based anomaly detection) with a hardware XOR encryption accelerator, both implemented in the FPGA fabric and exposed to the ARM Cortex-A9 processor through an AXI4-Lite memory-mapped interface. The system achieves sub-nanosecond encryption decisions with less than 0.02% LUT utilization on the xc7z020clg484-1 device. Behavioral simulation confirms correct ciphertext computation and accurate anomaly flagging across five boundary test cases, and bitstream generation completes with over 7 ns of positive setup slack at 100 MHz. The architecture is intentionally modular and parameterizable, providing a solid foundation for upgrading to production-grade AES encryption and hardware neural network-based anomaly detection in future work.