International Journal of Science, Engineering and TechnologyAuthors: Tambe Pranjal Machhindra, Bangar Abhishek Popat
Abstract: Energy dissipation, rather than transistor density, now limits the performance of general-purpose processors, and conventional complementary metal-oxide-semiconductor (CMOS) logic is approaching practical efficiency limits because every erased bit and every abruptly charged node releases energy as heat. Reversible computing addresses this problem by preserving information throughout a computation so that, when combined with adiabatic switching, most of the signal energy can in principle be recovered rather than dissipated. This paper presents a focused review of reversible logic-based architectures for ultra-low-power central processing units (CPUs). Literature drawn from IEEE Xplore, SpringerLink, ScienceDirect, American Physical Society and Nature Portfolio journals, and related sources is organized into four themes: thermodynamic foundations and reversible gate libraries; reversible instruction-set and processor architectures; physical implementation technologies, including adiabatic CMOS, adiabatic superconductor logic, ballistic fluxon logic and quantum-dot cellular automata; and evaluation practice. The comparative analysis shows that logically reversible processors have been specified and simulated, and that adiabatic superconductor microprocessors have been demonstrated, but no reviewed study reports measured system-level energy savings for a fully reversible CPU. Key gaps include efficient resonant power-clock generation, leakage and cryogenic overheads, garbage management and inconsistent evaluation metrics. A conceptual layered architecture is proposed to frame these challenges and guide future research.
