International Journal of Science, Engineering and TechnologyAuthors: G.Shanthi
Abstract: The growing demand for high-speed and low-power digital systems has intensified the need for optimized arithmetic circuits, particularly at advanced technology nodes. This paper presents a detailed comparative analysis of the Manchester Carry Chain Adder (MCCA) implemented using FinFET technology at the 14nm node. The MCCA is recognized for its efficient carry propagation and regular layout structure, making it an attractive option for high performance arithmetic operations. With the limitations of traditional planar CMOS becoming more prominent at sub-20nm nodes, FinFETs offer a viable alternative due to their superior electrostatic control, reduced short-channel effects, and lower leakage currents. Using Synopsys Custom Compiler and a 14nm FinFET Process Design Kit (PDK), the MCCA was designed and simulated to evaluate key performance parameters such as propagation delay, dynamic and static power consumption, and estimated layout area. Transient simulations were carried out to assess timing performance, while power analysis was conducted using realistic input patterns. The results indicate that the FinFET-based MCCA provides substantial improvements in terms of speed and power efficiency compared to traditional CMOS-based designs. Specifically, the reduction in propagation delay and dynamic power highlights FinFET’s suitability for nextgeneration energy-efficient computing systems. Furthermore, the compact nature of the FinFET layout contributes to area savings, making it highly favorable for integration in dense VLSI systems. This study demonstrates the effectiveness of combining advanced transistor technologies with proven arithmetic architectures, and underscores the role of modern EDA tools in facilitating accurate and efficient VLSI design at nanoscale technology nodes.
