International Journal of Science, Engineering and TechnologyAuthors: Mr.N.B.Jilani, Dr.P.Prasanna Murali Krishna, Perumalla Geeta Bharathi, Venna Leelavathi, Porumamilla Dharshini, Sure Anusha
Abstract: Based on the historical practice of Vedic multiplication, this proposed study details a large-number variant of the Vedic multiplier. Since it improves over the alternatives in terms of speed, area, hardware complexity, power consumption, and scalability, a Vedic multiplier is the way to go. While Xilinx is used for circuit design, the Modelsim tool is used for implementation using Verilog HDL. The Carry Save Adder, the Carry Lookahead Adder, and the Ripple Carry Adder are three 32-bit Vedic multiplier designs that are analyzed in this paper. They use different adder architectures. Around 0.082W was the power consumption of all three designs. With a latency of 26.466 ns and almost similar power usage, the 32-bit CLA-based Vedic multiplier was the quickest. The RCA-based multiplier outperformed all other Vedic multipliers in terms of area usage. Search Terms—Circuit Design, Power Consumption, Vedic Mathematics, Parallel Processing, and High-Speed Multiplication [4]. The procedure for practicing vedic multiplication is shown in Fig. 1. By dividing the multiplication operation into smaller, more manageable parts, this method offers a new solution to the problem. When compared to older multiplier designs, this may provide better results, particularly when taking into account the power and performance limitations of contemporary DSP systems.
DOI: https://doi.org/10.5281/zenodo.20392712
