International Journal of Science, Engineering and TechnologyAuthors: Dr.D.Satyanarayana, Dr.A.Ranganayakulu, pagadala Himanjali, Thota Lavanya, Sadu Snehalatha, Kappeta Madhavi
Abstract: Multipliers are crucial components for implementing algorithms for processing digital signals in hardware. When planning the architecture of a system as a whole, multiplier design is crucial. The floating-point format is preferred over the fixed-point representation for algorithms that need data with a dynamic range. However, designers have challenges with floating-point multipliers because to their enormous latency and space requirements. In this paper, we propose a spatially and temporally improved approach to floating point multiplication. The Mantissa multiplication, which is carried out by rapid tree multipliers, is the design bottleneck of the floating-point multiplier. The suggested architecture improved partial product reduction in mantissa multiplication by using Carry-lookahead adders as compressors, as opposed to half-adders and full-adders used in traditional Wallace or Dadda tree multipliers. Verilog HDL description is used to develop the FPGA and verify the suggested design. There was a 9.9 percentage point reduction in latency compared to Dadda and an 8.5% improvement compared to Wallace.
DOI: https://doi.org/10.5281/zenodo.20394359
