International Journal of Science, Engineering and TechnologyAuthors: Dr.D.Satyanarayana, Dr.A.Ranganayakulu, Maddasani Venkata Bala Krishnudu, Surarapu.V.V.Chandramohan Reddy, Challa Bhanu Prakash, Kola Bharath
Abstract: A 16-bit RISC processor with increased instruction execution capability via the use of Verilog and a Vedic multiplier design is the main focus of this study. For the purpose of design simulation, Vivado 2018.We utilize the 3D design suite. Applying the multiplier unit under the Arithmetic and logic unit (MAC) using the methods outlined in the Vedic Sutras is the primary objective of this study. Streamlining conventional computations in order to drastically reduce computing complexity is fundamental to Vedic mathematics. The data path allows information to move between different parts of the RISC processor, such as the memory, program counter, and register bank, and the control unit (which oversees the computer's operations) is another block that is part of the designed processor. The proposed RISC processor is quite simple and has the capability to carry out a grand total of fourteen commands. Compared to conventional ALU and MAC designs, this study successfully reduces power consumption in the Multiply-Accumulate (MAC) and arithmetic logic units (ALU) correspondingly. Both the Arithmetic Logic Unit (ALU) and the Multiply-Accumulate (MAC) have reduced delays as compared to their conventional counterparts. A 16-bit Vedic processor was born because of the gradual merging of the Vedic MAC and ALU with additional processing blocks. Compared to a regular CPU, this results in less delay and less power consumption. It follows that the most important characteristics of a well-designed CPU are a reduction in power consumption, an increase in operating speed, and smaller footprint. Verilog HDL, Vedic Mathematics, Von-Neumann architecture, Reduced Instruction Set Computer, and Sutras.
DOI: https://doi.org/10.5281/zenodo.20394625
