International Journal of Science, Engineering and TechnologyAuthors: R.Ananthakrishnan, Sanjeeva Kumar Vudi
Abstract: The advent of intelligent edge devices from implantable biosensors to autonomous micro-robots has highlighted the inherent energy inefficiency of traditional von Neumann architectures when running dense neural network inference workloads. The bio-inspired concept of neuromorphic computing, which leverages the event-driven and sparse nature of information propagation in biological nervous systems, represents a promising approach to achieve intelligence at the milliwatt scale. In this paper, we provide an organized study of the design considerations, tradeoffs, and performance of neuromorphic hardware architectures designed for ultra-low power inference. We discuss execution models for spiking neural networks, hardware implementations ranging from digital, through mixed-signal, to memristive circuits, and introduce a reference architecture that jointly optimizes neuron dynamics, synaptic weight storage, and event-driven communication. Our quantitative analysis over benchmark datasets in silicon shows that event-driven execution on neuromorphic substrates enables orders-of-magnitude reductions in dynamic energy compared to traditional edge accelerators while retaining good inference performance and sub-10ms latency.
DOI: https://doi.org/10.5281/zenodo.23906786
