Optimized Low Power 8-bit Array Multiplier With CSA And CLA

Authors: Rallabandi Shruthi, Dasania Prashanth, Nittala Sesha HariHara kumar, K. Thrisandhya

Abstract: This paper presents an optimized design of an 8-bit array multiplier optimized for superior performance and reduced power usage. While conventional array multipliers are straightforward to design, they often suffer from high propagation delays and excessive power demands. The proposed design integrates Carry Save Adders (CSA) for parallel partial product summation and Carry Look-Ahead Adders (CLA) for efficient final addition. Simulations confirm the design's improved speed, lower power consumption, and better area efficiency, making it an ideal choice for mobile and embedded applications. The architecture was implemented using Verilog HDL and validated with Xilinx Vivado tools on the Artix7 platform, demonstrating its practicality The design is implemented in Verilog HDL and simulated using Xilinx Vivado, showcasing the practical viability of the architecture.

DOI: http://doi.org/