Simulation And Implementation Of Hybrid Error Correction Codes For Space Applications

6 Jun

Authors: Shaik Jani Begum, J Ravisankar

Abstract: This research aims to develop a new EDAC system that can detect and repair mistakes in space-grade onchip memory produced by cosmic radiation and multi-cell disturbances in extreme environments. Traditional XOR-based two-dimensional codes have a data width that may vary between 32 and 64 bits, limiting them to single-bit or restricted multi-bit protection. In contrast, the proposed approach provides far wider fault coverage. The verification procedure of block-wise XOR redundancy and cyclic redundancy check (CRC) efficiently addresses issues like burst faults by leveraging the diagonals, parity, and creation of the check-bit. The decoding process employs the encrypted 64-bit input to recover the original 32-bit data, allowing for full data recovery with high accuracy. After we develop and synthesize the design in Xilinx Vivado to test efficiency, we will go into power consumption, LUT utilisation, flip-flop deployment, and I/O efficiency in depth. The experimental findings suggest that the approach provides high resilience at minimal redundancy, together with lightweight protection for memory in aircraft systems, and outstanding dependability. In addition, we have introduced a hybrid CRC-XOR coding and signaling scheme that strikes a balance between error resilience and minimal hardware overhead utilisation, we have ensured that the recovery still returns 32 bits when scaling to 32-bit inputs, and we have explicitly supported burst errors through error correction.

DOI: http://doi.org/10.5281/zenodo.20569606