International Journal of Science, Engineering and TechnologyAuthors: Pratikbhai Patel
Abstract: The fast paced growth of the international digital infrastructure has also heightened the need to have safe and high-performance cryptographic frameworks that are able to safeguard sensitive data in large scale data centres and distributed computing setting. Cryptographic processors implemented in hardware via application of Very Large Scale Integration (VLSI) technology can be highly beneficial in encryption speed, energy consumption, and system security as opposed to encryption methods in software. The study explores the design and analysis of VLSI architecture of putting into practice Application-Specific Integrated Circuit (ASIC) cryptographic hardware with the use of AES-256 encryption algorithm. The paper analyzes hardware architectural designs applied in AES-256 processors and discusses the important performance metrics such as the throughput of encryption process, the power usage, the silicon area, and resilience to security. The comparison of ASIC and FPGA cryptography platforms is also analyzed to find the best hardware platforms to use in high-performance encryption systems. Supportively, the study considers hardware security risks such as side-channel attacks, and hardware Trojans that are capable of weakening cryptographic processors used in the international computing infrastructure. The results underscore the relevance of energy-efficient hardware architectures and built-in security countermeasures in the development of secure cryptographic processors that can support the current data centre activities. The paper finds that optimised ASIC- based AES-256 architectures present a trade-off solution in the need to address a strong encryption security and efficient power consumption in the large-scale digital system.
DOI: https://doi.org/10.5281/zenodo.19088949
