VLSI-Based Power-Efficient Booth Multiplier for IoT Applications in FPGA Systems

VLSI-Based Power-Efficient Booth Multiplier for IoT Applications in FPGA Systems

Authors- M.Tech. Scholar Ms. Mansi Yadav, Assistant Professor Mrs. Deepali Sahu

Abstract-As the Internet of Things (IoT) continues to expand, the need for energy-efficient and high-performance hardware becomes critical, particularly for embedded systems where power and resource constraints are paramount. Multiplication is a fundamental operation in many IoT applications, and traditional Booth multipliers, while efficient in reducing the number of partial products, often consume significant power. This research addresses this challenge by proposing a VLSI-based power-efficient Booth multiplier specifically optimized for FPGA systems utilized in IoT applications. The proposed design implements advanced techniques to minimize power consumption without sacrificing computational speed or accuracy. Key optimizations include reducing switching activity, improving data path efficiency, and minimizing unnecessary signal transitions, resulting in a significant reduction in overall energy usage. The architecture is synthesized and implemented on FPGA platforms, ensuring flexibility, scalability, and compatibility with IoT hardware constraints. Performance metrics such as power consumption, area utilization, and operating speed are analyzed and compared to conventional Booth multipliers and other low-power designs. The results demonstrate that the proposed design achieves a significant reduction in power consumption while maintaining high throughput, making it a suitable solution for power-sensitive IoT environments where energy efficiency is critical. This research contributes to the development of more sustainable and high-performance hardware architectures for the next generation of IoT devices.

DOI: /10.61463/ijset.vol.13.issue1.112