International Journal of Science, Engineering and TechnologyAuthors: Akshata Bagewadi, Anirudh patil, Nandan Hebbar, Naveena Kittur, Deepak Sharma
Abstract: As VLSI technology scales, the demand for area-efficient and high-speed arithmetic circuits increases. This research investigates the performance characteristics of 8-bit Vedic and Wallace Tree multipliers designed at the 45nm technology node. The study introduces a comparative framework between standard Traditional CMOS design rules and a modified Transmission Gate (TG) technique, where basic AND/OR gates are optimized using only three transistors to reduce footprint. Detailed schematics were developed for both architectures: the Vedic multiplier utilizes a modular approach with Ripple Carry Adders (RCAs) for intermediate sum reduction, while the Wallace multiplier employs a parallel reduction tree consisting of 48 Full Adders and 8 Half Adders. Simulation results reveal distinct performance advantages for each logic style. The proposed 3-transistor TG method significantly reduced the transistor count, with the TG-based Wallace and Vedic designs requiring only 1,720 and 2,524 transistors, respectively. Conversely, the Traditional CMOS designs demonstrated superior signal integrity and power efficiency. The Traditional Wallace Multiplier outperformed all other variations, recording a delay of 0.12 ns and power consumption of 11.27 µW. The analysis suggests that for 45nm node designs where power-delay product (PDP) is the primary constraint, the Traditional Wallace structure is preferable, whereas the TG-based approach is viable for strictly area-constrained applications.
