International Journal of Science, Engineering and TechnologyAuthors: Dr.A.Ranganayakulu, Dr.D.Satyanarayana, Venna Kasieswari, Dudekula Rijvana, Duddela Ramya, Shaik Farida
Abstract: A single-cycle processor with support for 30 instructions based on the RV32I instruction set architecture (ISA) is presented in this research. Because it was necessary to fetch, decode, execute, and finish each instruction within one clock cycle, the single-cycle architecture was selected. When simplicity and power economy are more important than execution speed, this strategy works well for small-scale applications. Important parts of the architecture include a data memory for storing information, an arithmetic logic unit (ALU) for performing logical and mathematical operations, a register file for storing instructions, and instruction memory for storing data. In order to control the flow of data and make sure instructions are executed correctly, control signals are created depending on the opcode. The Verilog hardware description language (HDL) was used in the development of the CPU. As a platform for implementation, the Arty-S7-FPGA board was the goal of the design synthesis. Basic processes including data transmission, math computations, and control flow are effectively handled by the architecture. The test bench is built using verilog and all thirty instructions are tested in the Vivado software environment for operation verification. This research explores the RISC-V architecture from the bottom up and paves the way for improved implementations of pipelined processors in the future. Nouns: Vivado, Verilog, Single-Cycle Processor, RV32I Instruction Set Architecture.
DOI: https://doi.org/10.5281/zenodo.20392389
