International Journal of Science, Engineering and TechnologyAuthors: Murari Kumar, Associate Professor Dr. Deepti Shinghal
Abstract: High-speed and low-noise comparators are essential building blocks of modern analog-to-digital converters (ADCs), where propagation delay, noise, offset voltage, power consumption, and circuit complexity directly influence the overall conversion performance. This paper presents the design and simulation of a high-speed, low-noise dynamic CMOS comparator intended for high-performance analog and mixed-signal applications. A comparative analysis of conventional dynamic latch-based, double-tail latch-based sense-amplifier, uncalibrated dynamic, and reconfigurable dynamic comparator architectures is performed using key performance parameters including propagation delay, operating speed, RMS noise, offset voltage, slew rate, and transistor count. The proposed architecture incorporates a differential amplifier stage within the regenerative latch and employs optimized clocking to improve signal integrity and decision speed. The design is evaluated using LTspice IV with a 50 nm CMOS technology model. Simulation results indicate a minimum propagation delay of 0.650 ns, corresponding to a maximum operating speed of 1.538 GHz. The proposed comparator also achieves an RMS noise of 704.38 µV while using 13 transistors. The results demonstrate a balanced trade-off between speed, noise performance, and circuit complexity. The proposed architecture can therefore serve as a suitable comparator core for high-speed ADCs and other low-power mixed-signal systems.
